Microprocessor Architectures for Web Networks: A Review of SmartNICs, DPUs, and Heterogeneous Computing Platforms

الملخص

The rapid growth of cloud computing, hyperscale data centers, artificial intelligence services, and programmable web infrastructures has significantly transformed the design requirements of modern microprocessors. Traditional server-centric architectures based solely on general-purpose CPUs are increasingly challenged by the rising demands of networking, virtualization, storage management, and large-scale distributed computing workloads. This paper presents a systematic review of microprocessor architectures for modern web networks, with emphasis on heterogeneous computing platforms integrating infrastructure-class CPUs, SmartNICs, Data Processing Units (DPUs), and programmable network processors. The study reviews recent developments in cloud-oriented processor architectures such as Arm Neoverse, NVIDIA Grace, and Google Axion, alongside emerging SmartNIC and DPU technologies designed for infrastructure offloading and programmable data-plane acceleration. The reviewed architectures are comparatively analyzed in terms of throughput, latency, energy efficiency, scalability, programmability, and infrastructure offloading capability. The study further discusses the role of programmable networking technologies in enabling adaptive packet processing, virtualization, security enforcement, and AI-assisted web services. The review demonstrates that heterogeneous and network-centric computing architectures provide substantial improvements in scalability, resource utilization, and cloud-service efficiency compared with conventional host-centric systems. Finally, current challenges and future research directions are highlighted, including interoperability, orchestration complexity, security management, and the integration of AI-native acceleration technologies within next-generation web-network infrastructures.